FIG. 7 is the cross sectional view of general planar SBD 100.
SBD 100 includes n+-type semiconductor substrate 1, n-type semiconductor layer 2 grown epitaxially on semiconductor substrate 1, anode electrode 3 coated on semiconductor layer 2 for forming a Schottky junction with semiconductor layer 2, and cathode electrode 4 on the back surface of n+-type semiconductor substrate 1 for forming an ohmic contact with semiconductor substrate 1. SBD 100 further includes a p-type semiconductor region as guard ring 5 in the surface portion of semiconductor substrate 1 in the edge area of the Schottky junction section. Guard ring 5 is in contact with a part of anode electrode 3. Insulator film 6 is coated from the device edge side surface of guard ring 5 to the outer edge of n-type semiconductor layer 2.
Generally, it is possible to control the barrier height in the junction plane between the anode electrode and the n-type semiconductor layer in the SBD by changing the anode electrode material. It is possible to set the built-in potential in the SBD to be lower than the built-in potential in the general pn-diode. Since no minority carrier accumulation occurs in the SBD fundamentally, the SBD switches advantageously at a high-speed with a low switching loss. However, a high leakage current is caused in the SBD, when a reverse bias voltage is applied. Since no conductivity modulation occurs in the SBD, the ON-state resistance in the SBD exhibiting a high breakdown voltage becomes higher than the ON-state resistance in the pn-diode, when a high current is made to flow therein.
It is well known that there exists a tradeoff relation between the ON-state resistance and the leakage current in the SBD. The ON-state resistance of the n-type semiconductor layer may be lowered by increasing the impurity concentration therein. However, it is hard for the depletion layer expanding from the Schottky junction to expand into the n-type semiconductor layer and the electric field strength in the vicinity of the Schottky junction reaches the critical electric field strength of silicon easily under a low reverse bias voltage applied, resulting in a low breakdown voltage. Further, since the surface electric field strength becomes stronger in the edge area of the anode electrode and in the vicinity thereof, the leakage current increases.
In the SBD, in which the impurity concentration in n-type semiconductor layer 2 is low, a high breakdown voltage is obtained and the leakage current caused is low. However, the ON-state resistance becomes high and losses increase.
In SBD 100 described with reference to FIG. 7, in which a p-type semiconductor region is used as guard ring 5, guard ring 5 will operates as a pn-diode, if the applied voltage exceeds the built-in potential to the higher side in turning SBD 100 on. Due to the pn-diode operation of guard ring 5, it takes a time to eject the accumulated minority carriers in shifting SBD 100 from the ON-state thereof to the OFF-state thereof. Therefore, the reverse recovery time (Trr) is elongated and SBD 100 is prevented from conducting high-speed operations.
The following Non-Patent Document 1 reports a trench MOS barrier Schottky (hereinafter referred to as “TMBS”) rectifier for improving the tradeoff relations caused in the SBD described above. As one of the TMBS diodes, the following Patent Document 1 discloses a TMBS diode including a trench MOS gate structure in the surface thereof as shown in FIG. 8.
TMBS diode 101 shown in FIG. 8 includes a MOS-gate-like structure including trenches 7 formed in the surface portion of a semiconductor substrate, insulator film 8 on the trench 7 inner wall, and electrically conductive material 9 such as polysilicon in the space surrounded by insulator film 8. Trenches 7 are spaced apart from each other for an equal spacing. In the TMBS diode provided with the MOS-gate-like structure as described above, n-type semiconductor layer 2 works as a current path that makes a drift current flow vertically in the ON-state of the TMBS diode. Since a depletion layer expands also from the MOS gate, when a reverse bias voltage is applied, a pinch-off effect is obtained. Due to the pinch-off effect, the electric field in the semiconductor surface is relaxed, the breakdown voltage is improved, and the leakage current is reduced. By adjusting the spacing between trenches 7 and the impurity concentration in n-type semiconductor layer 2, a lower ON-state resistance is obtained in the TMBS diode at a leakage current equivalent to the leakage current caused in the usual planar diode that includes no trench.
The following Patent Documents 2 and 3 disclose TMBS diodes which have a structure including an edge termination trench, a thick insulator film in the edge termination trench, and a field plate on the thick insulator film for improving the breakdown voltage.    [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2002-50773    [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2002-208711    [Patent Document 3] Published Japanese Translation of PTC International Publication for Patent Application No. 2008-533696    [Non-Patent Document 1] M. MEHROTRA and B. J. BALIGA, “Trench MOS Barrier Schottky (TMBS) Rectifier: A Schottky Rectifier with Higher than Parallel Plane Breakdown Voltage”, Solid State Electronics, vol. 38, No. 4 (1995), pp. 801-806
The TMBS structure as disclosed in the Patent Document 1 poses the problem described below.
In the TMBS structure shown in FIG. 8, the breakdown voltage thereof peaks at the predetermined spacing between trenches 7 (at the predetermined mesa region 10 width) as described in FIG. 9. For increasing the device breakdown voltage, it is desirable to design the spacing between trenches 7 at the peak breakdown voltage. However, if the trench 7 spacing is designed at the peak breakdown voltage, the electric field will localize to the location A in the vicinity of the lower portion of an insulator film on the side wall of outermost edge-termination trench 7 in the chip edge area, when a reverse bias voltage is applied. Due to the electric field localization to the location A, breakdown is caused at the location A prior to the breakdown in the Schottky junction section (active section) in the TMBS structure, lowering the breakdown voltage. For obtaining a higher breakdown voltage, the breakdown voltage in the edge termination trench should be made to be higher than the breakdown voltage in the active section.
For obviating the problem described above, the Patent Documents 2 and 3 propose to provide the edge termination trench with a field plate structure. However, the edge termination trench having a field plate structure poses the problems described below.
It is necessary for the manufacture of the TMBS diode disclosed in the Patent Document 2 to pattern and etch an oxide film on the narrow spacer in the edge termination trench. Therefore, it is very difficult to perform the step of pattern etching. Since it is difficult to secure a certain process margin in providing the edge termination trench with a field plate structure, it is hazardous to realize a stable manufacturing process.
It is necessary for the TMBS diode disclosed in the Patent Document 3 to thicken the oxide film in the trench bottom by thermal oxidation. However, since it is very difficult for the thermal oxidation technique to form an oxide film of 1 μm or more in thickness, there exists a certain limitation in obtaining a higher breakdown voltage.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a method of manufacturing a semiconductor device including a trench MOS gate structure that facilitates relaxing the electric field strength in the vicinity of the Schottky junction under a reverse bias voltage applied. It would be further desirable to provide a method of manufacturing a semiconductor device that facilitates thickening the insulator film in the bottom of a ring-shaped edge termination trench surrounding the trench MOS gate structure to sustain a stronger electric field. It would be further desirable to provide a method of manufacturing a semiconductor device that includes an edge termination structure that exhibits a higher breakdown voltage.